1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus configured to transfer data to a plurality of shift registers.
2. Description of the Related Art
In a case where data is transferred between two shift registers each being composed of flip-flop circuits, in general, the data is transferred in synchronism with a common clock signal. However, in a case where there exists certain long data or clock transfer lines as compared with a period of the clock signal between two shift registers, there is a large problem with a transfer delay caused by a resistance and a capacity of these lines or a capacity between the adjacent lines, so that a circuit design becomes difficult.
In order to solve this problem, there is a method for transferring data from one shift register to another shift register in an asynchronous manner. This method includes the following steps.
First, data is sent from a shift register of a sending side to a shift register of a receiving side. When data receiving is completed in the receiving side shift register, a reception acknowledge signal is started and sent to the sending side shift register which terminates the data sending when the reception acknowledge signal is received. In the data receiving side, the sending of the reception acknowledge signal is terminated when the termination of the data sending is detected. When the termination of the reception acknowledge signal is detected in the data sending side, following data is sent to the receiving side shift register. This data sending operation is repeated for number of times corresponding to the number of bits between the data sending and receiving side shift registers.
When the reception acknowledge signal transmitted from the receiving side shift register to the sending side shift register is used in the receiving side as a clock signal to shift the data received from the sending side shift register and when the same acknowledge signal is used in the sending side as the clock signal to shift the data being sent to the receiving side shift register, it is possible to transfer the data reliably in an asynchronous mode irrespective of a length of a data transfer line from the sending side to the receiving side.
However, in a case where a plurality of receiving side shift registers exist on a semiconductor chip, for example, and these registers are connected to transmitting side shift registers via data transfer lines having different delay times from each other, even if the receiving side shift registers are connected in series, a transfer error caused by a dispersion of a transmission delay between the receiving shift registers is likely to occur, making it difficult to reliably transfer data.